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NAND08GW3C2A NAND16GW3C4A
8/16 Gbit, 2112 byte page, 3 V supply, multilevel, multiplane, NAND Flash memory
Features
High density multilevel cell (MLC) Flash memory - Up to 16 Gbit memory array - Up to 512 Mbit spare area - Cost-effective solutions for mass storage applications NAND interface - x 8 bus width - Multiplexed address/data Supply voltage: VDD = 2.7 to 3.6 V Page size: (2048 + 64 spare) bytes Block size: (256K + 8K spare) bytes Multiplane architecture - Array split into two independent planes - Program/erase operations can be performed on both planes at the same time Page read/program - Random access: 60 s (max) - Sequential access: 25 ns (min) - Page program operation time: 800 s (typ) Multipage program time (2 pages): 800 s (typ) Fast block erase - Block erase time: 2.5 ms (typ) Multiblock erase time (2 blocks): 2.5 ms (typ) Status register Electronic signature Serial number option Chip enable `don't care'

TSOP48 12 x 20 mm (N)

LGA52 12 x 17 mm (N)
Data protection - Hardware program/erase locked during power transitions Development tools - Error correction code models - Bad block management and wear leveling algorithm - HW simulation models Data integrity - 10,000 program/erase cycles (with ECC) - 10 years data retention ECOPACK(R) packages available

January 2008
Rev 2
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www.numonyx.com 1
NAND08GW3C2A, NAND16GW3C2A
Contents
1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1 Bad blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 Inputs/outputs (I/O0-I/O7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Address Latch Enable (AL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Command Latch Enable (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Chip Enable (E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Read Enable (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Ready/Busy (RB1, RB2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 VDD supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1 4.2 4.3 4.4 4.5 4.6 Command Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Address Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5 6
Command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1 6.2 6.3 6.4 Read Memory Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Random Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Page Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Page Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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NAND08GW3C2A, NAND16GW3C2A
6.5 6.6 6.7 6.8 6.9 6.10 6.11
Sequential Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Random Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Multiplane Page Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Block Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Multiplane Block Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Read Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.11.1 6.11.2 6.11.3 Write protection bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 P/E/R controller bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Error bit (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.12 6.13
SR5, SR4, SR3, SR2 and SR1 bits are reserved . . . . . . . . . . . . . . . . . . . 29 Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7 8 9
Concurrent operations and ERS on the NAND16GW3C2A . . . . . . . . . 32 Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Software algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.1 9.2 9.3 9.4 9.5 Bad block management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 NAND Flash memory failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Wear-leveling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Hardware simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.5.1 9.5.2 Behavioral simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 IBIS simulations models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
10 11 12
Program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 38 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
12.1 12.2 Ready/Busy signal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 52 Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
13
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
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NAND08GW3C2A, NAND16GW3C2A
14 15
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
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NAND08GW3C2A, NAND16GW3C2A
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Valid blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Address insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Address definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Status Register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Electronic signature byte 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Electronic signature byte 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Electronic signature byte 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Extended Read Status Register commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Block failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Program and erase times and program erase endurance cycles . . . . . . . . . . . . . . . . . . . . 38 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 AC characteristics for command, address, data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 AC characteristics for operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package mechanical data. . . . . 54 LGA52 12 x 17 mm, 1 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . 55 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
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NAND08GW3C2A, NAND16GW3C2A
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Logic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 TSOP48 connections for NAND08GW3C2A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 TSOP48 connections for NAND16GW3C4A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 ULGA52 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Random data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Page Program operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Random Data Input during Sequential Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Multiplane Page Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Block Erase operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Multiplane Block Erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Bad block management flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Command latch AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Address latch AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Data input latch AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Sequential data output after Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Sequential data output after Read AC waveforms (EDO mode). . . . . . . . . . . . . . . . . . . . . 46 Read Status Register AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Read electronic signature AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Page Read operation AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Page Program AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Block Erase AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Reset AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Program/Erase Enable waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Program/Erase Disable waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Ready/Busy AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Ready/Busy load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Resistor value versus waveform timings for Ready/Busy signal. . . . . . . . . . . . . . . . . . . . . 53 Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline . . . . . . . . . . . . 54 LGA52 12 x 17 mm, 1 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
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NAND08GW3C2A, NAND16GW3C2A
Description
1
Description
The NAND08GW3C2A and NAND16GW3C2A are multilevel cell (MLC) devices from the NAND Flash 2112-byte page family of non-volatile Flash memories. The NAND08GW3C2A and the NAND16GW3C2A have a density of 8- and 16-Gbit, respectively. The NAND16GW3C2A is composed of two 8-Gbit dice; each die can be accessed independently using two Chip Enable and two Ready/Busy signals. The devices operate from a 3 V VDD power supply. The address lines are multiplexed with the Data Input/Output signals on a multiplexed x8 input/output bus. This interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint. Each block can be programmed and erased over 10,000 cycles (with ECC on). The device also has hardware security features; a write protect pin is available to give hardware protection against Program and Erase operations. The devices feature an open-drain, ready/busy output that can be used to identify if the Program/Erase/Read (P/E/R) Controller is currently active. The use of an open-drain output allows the ready/busy pins of several memories to be connected to a single pull-up resistor. The memory array is split into 2 planes of 2048 blocks each. This multiplane architecture makes it possible to program 2 pages at a time (one in each plane) or to erase 2 blocks at a time (one in each plane), dividing by two the average program and erase times. The devices have the Chip Enable "Don't Care" feature, which allows code to be directly downloaded by a microcontroller, as Chip Enable transitions during the latency time do not stop the Read operation. There is the option of a unique identifier (serial number), which allows the NAND08GW3C2A and the NAND16GW3C2A to be uniquely identified. It is subject to an NDA (non-disclosure agreement) and is, therefore, not described in the datasheet. For more details of this option contact your nearest Numonyx Sales office. The devices are available in TSOP48 (12 x 20 mm) and LGA52 (12 x 17 x 0.65 mm) packages. To meet environmental requirements, Numonyx offers the devices in ECOPACK(R) packages. ECOPACK packages are lead-free. In compliance with JEDEC Standard JESD97, the category of second level interconnect is marked on the package and on the inner box label. The maximum ratings related to soldering conditions are also marked on the inner box label. The devices are shipped from the factory with block 0 always valid and the memory content bits, in valid blocks, erased to `1'. Refer to the list of available part numbers and to Table 24: Ordering information scheme for information on how to order these options.
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Description Table 1. Device summary
NAND08GW3C2A, NAND16GW3C2A
Timings Part number Density Bus width Page size Block size Operatin Random Memory Page Sequentia g voltage access array l access program (VDD) time (typ) time (min) (max) 128 pages x 4096 blocks 128 pages x 8192 blocks Block erase (typ) Package
NAND08GW3 C2A
8 Gb x8 2048+ 64 bytes 256 K +8K bytes
TSOP48 ULGA52 2.7 to 3.6 V 60 s 25 ns 800 s 2.5 ms TSOP48 ULGA52
NAND16GW3 C4A(1)
16 Gb
1. The NAND16GW3C2A is composed of two 8-Gbit dice.
Figure 1.
Logic block diagram
Address register/counter AL CL W E1 E2 WP R X Decoder
Command interface logic
P/E/R controller high voltage generator
NAND Flash memory array
Page buffer Command register Y decoder
Data register
Buffers RB1 RB2 I/O
AI13296b
1. E2 and RB2 are only present in the NAND16GW3C4A.
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NAND08GW3C2A, NAND16GW3C2A Figure 2. Logic diagram
Description
VDD
E1 E2 R W AL CL WP VSS NAND Flash
I/O0 - I/O7 x8
RB1 RB2
AI13632b
1. E2 and RB2 are only present in the NAND16GW3C4A.
Table 2.
Signal names
Function Data input/outputs(1) Command Latch Enable Address Latch Enable Chip Enable(2) Read Enable Write Enable Write Protect Ready/Busy (open drain output)(2) Power supply Ground No connection Do not use Input/output Input Input Input Input Input Input Output Power supply Ground Direction
Signal I/O0 - I/O7 CL AL E1, E2 R W WP RB1, RB2 VDD VSS NC DU
1. On the LGA52 package, each 8-Gbit die is accessed and controlled via two sets of I/Os and control signals. 2. E2 and RB2 are only present in the NAND16GW3C4A.
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Description Figure 3.
NAND08GW3C2A, NAND16GW3C2A TSOP48 connections for NAND08GW3C2A
NC NC NC NC NC NC RB R E NC NC VDD VSS NC NC CL AL W WP NC NC NC NC NC
1
48
NAND Flash 12 13 37 36
NC NC NC NC I/O7 I/O6 I/O5 I/O4 NC NC NC VDD VSS NC NC NC I/O3 I/O2 I/O1 I/O0 NC NC NC NC
24
25
AI13633
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NAND08GW3C2A, NAND16GW3C2A Figure 4. TSOP48 connections for NAND16GW3C4A
Description
NC NC NC NC NC RB2 RB1 R E1 E2 NC VDD VSS NC NC CL AL W WP NC NC NC NC NC
1
48
12 37 NAND FLASH 13 36
NC NC NC NC I/O7 I/O6 I/O5 I/O4 NC NC NC VDD VSS NC NC NC I/O3 I/O2 I/O1 I/O0 NC NC NC NC
24
25
AI13169
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Description Figure 5. ULGA52 connections
NAND08GW3C2A, NAND16GW3C2A
0
1
2
3
4
5
6
7
8
OA
NC NC CL1 VSS AL1 CL2 AL2 W2 WP1 I/O02 I/O11 I/O12 I/O21 I/O31 I/O22 VSS VSS NC I/O32 I/O42 I/O41 VDD NC I/O61 I/O51 I/O52 I/O01 WP2 I/O71 I/O62 W1 RB1 VSS I/O72 E2 R2 RB2 E1 VDD R1 NC
NC A NC B C NC D E F G H J NC K L M N
OB
NC
OC
NC
OD
NC
OE
NC
NC
OF
NC
NC
AI13634
1. On the LGA52 package, each 8-Gbit die is accessed and controlled via two sets of signals.
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NAND08GW3C2A, NAND16GW3C2A
Memory array organization
2
Memory array organization
The memory array is comprised of NAND structures where 32 cells are connected in series. The memory array is organized in blocks where each block contains 128 pages. The array is split into two areas, the main area and the spare area. The main area of the array is used to store data, whereas the spare area is typically used to store software flags or bad block identification. The pages are split into a 2048-byte main area and a spare area of 64 bytes. Refer to Figure 6: Memory array organization.
2.1
Bad blocks
The NAND08GW3C2A and NAND16GW3C2A devices may contain bad blocks, where the reliability of blocks that contain one or more invalid bits is not guaranteed. Additional bad blocks may develop during the lifetime of the device. The bad block Information is written prior to shipping (refer to Section 9.1: Bad block management for more details). Table 3: Valid blocks shows the minimum number of valid blocks in each device. The values shown include both the bad blocks that are present when the device is shipped and the bad blocks that could develop later on. These blocks need to be managed using Bad Blocks Management and Block Replacement (refer to Section 9: Software algorithms). Table 3. Valid blocks(1)
Density of device 8 Gbits 16 Gbits Minimum 4016 8032 Maximum 4096 8192
1. The NAND16GW3C4A is composed of two 8-Gbit dice. The minimum number of valid blocks is 4096 for each die.
13/58
Memory array organization Figure 6. Memory array organization
x8 bus width Plane = 2048 blocks Block = 128 Pages Page = 2112 Bytes (2,048 + 64)
NAND08GW3C2A, NAND16GW3C2A
First Plane
Second Plane
a Sp
Main Area Block Page
re
Are
a re pa Are a
S
Main Area
8 bits 2048 Bytes 64 Bytes 2048 Bytes 64 Bytes
Page Buffer, 2112 Bytes 2,048 Bytes
64 Bytes
Page Buffer, 2112 Bytes 2,048 Bytes
64 Bytes
8 bits
2 Page Buffer, 2x 2112 Bytes
AI13170
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NAND08GW3C2A, NAND16GW3C2A
Signal descriptions
3
Signal descriptions
See Figure 1: Logic block diagram, and Table 2: Signal names, for a brief overview of the signals connected to this device.
3.1
Inputs/outputs (I/O0-I/O7)
Input/outputs 0 to 7 are used to input the selected address, output the data during a Read operation, or input a command or data during a Write operation. The inputs are latched on the rising edge of Write Enable. I/O0-I/O7 are left floating when the device is deselected or the outputs are disabled.
3.2
Address Latch Enable (AL)
The Address Latch Enable activates the latching of the address inputs in the command interface. When AL is High, the inputs are latched on the rising edge of Write Enable.
3.3
Command Latch Enable (CL)
The Command Latch Enable activates the latching of the command inputs in the command interface. When CL is High, the inputs are latched on the rising edge of Write Enable.
3.4
Chip Enable (E1, E2)
The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is Low, VIL, the device is selected. If Chip Enable goes High, vIH, while the device is busy, the device remains selected and does not go into standby mode. E2 is only available on the NAND16GW3C4A.
3.5
Read Enable (R)
The Read Enable pin, R, controls the sequential data output during Read operations. Data is valid tRLQV after the falling edge of R. The falling edge of R also increments the internal column address counter by one.
3.6
Write Enable (W)
The Write Enable input, W, controls writing to the command interface, input address and data latches. Both addresses and data are latched on the rising edge of Write Enable. During power-up and power-down a recovery time of 10 s (min) is required before the command interface is ready to accept a command. It is recommended to keep Write Enable High during the recovery time.
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Signal descriptions
NAND08GW3C2A, NAND16GW3C2A
3.7
Write Protect (WP)
The Write Protect pin is an input that gives a hardware protection against unwanted Program or Erase operations. When Write Protect is Low, VIL, the device does not accept any Program or Erase operations. It is recommended to keep the Write Protect pin Low, VIL, during power-up and power-down.
3.8
Ready/Busy (RB1, RB2)
The Ready/Busy output, RB, is an open-drain output that can be used to identify if the P/E/R controller is currently active. When Ready/Busy is Low, VOL, a Read, Program or Erase operation is in progress. When the operation completes, Ready/Busy goes High, VOH. The use of an open-drain output allows the Ready/Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy. During power-up and power-down a minimum recovery time of 10 s is required before the command interface is ready to accept a command. During this period the Ready/Busy signal is Low, VOL. RB2 is only available on the NAND16GW3C4A. Refer to Section 12.1: Ready/Busy signal electrical characteristics for details on how to calculate the value of the pull-up resistor.
3.9
VDD supply voltage
VDD provides the power supply to the internal core of the memory device. It is the main power supply for operations (Read, Program and Erase).
3.10
VSS ground
Ground, VSS, is the reference for the power supply. It must be connected to the system ground.
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NAND08GW3C2A, NAND16GW3C2A
Bus operations
4
Bus operations
There are six standard bus operations that control the memory. Each of these is described in this section. See the summary in Table 4: Bus operations. Typically, glitches of less than 5 ns on Chip Enable, Write Enable and Read Enable are ignored by the memory and do not affect bus operations.
4.1
Command Input
Command Input bus operations are used to give commands to the memory. Commands are accepted when Chip Enable is Low, Command Latch Enable is High, Address Latch Enable is Low and Read Enable is High. They are latched on the rising edge of the Write Enable signal. Only I/O0 to I/O7 are used to input commands. See Figure 16 and Table 20 for details of the timings requirements.
4.2
Address Input
Address Input bus operations are used to input the memory addresses. Five bus cycles are required to input the addresses (refer to Table 5: Address insertion). The addresses are accepted when Chip Enable is Low, Address Latch Enable is High, Command Latch Enable is Low and Read Enable is High. They are latched on the rising edge of the Write Enable signal. Only I/O0 to I/O7 are used to input addresses. See Figure 17 and Table 20 for details of the timings requirements.
4.3
Data Input
Data Input bus operations are used to input the data to be programmed. Data is only accepted when Chip Enable is Low, Address Latch Enable is Low, Command Latch Enable is Low and Read Enable is High. The data is latched on the rising edge of the Write Enable signal. The data is input sequentially using the Write Enable signal. See Figure 18 and Table 20 for details of the timing requirements.
4.4
Data Output
Data Output bus operations are used to read: the data in the memory array, the status register, the electronic signature and the unique identifier. Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is Low, and Command Latch Enable is Low. The data is output sequentially using the Read Enable signal. If the Read Enable pulse frequency is lower then 33 MHz (tRLRL higher than 30 ns), the output data is latched on the rising edge of Read Enable signal (see Figure 19).
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Bus operations
NAND08GW3C2A, NAND16GW3C2A
For higher frequencies (tRLRL lower than 30 ns), the Extended Data Out (EDO) mode must be considered. In this mode, data output is valid on the input/output bus for a time of tRLQX after the falling edge of Read Enable signal (see Figure 20). See Table 21 for details on the timings requirements.
4.5
Write Protect
Write Protect bus operations are used to protect the memory against Program or Erase operations. When the Write Protect signal is Low the device does not accept Program or Erase operations, therefore, the contents of the memory array cannot be altered. The Write Protect signal is not latched by Write Enable to ensure protection, even during power-up.
4.6
Standby
The memory enters Standby mode by driving Chip Enable, E, High. In Standby mode, the device is deselected, outputs are disabled and power consumption is reduced.
Table 4.
Bus operations
E VIL VIL VIL VIL X VIH AL VIL VIH VIL VIL X X CL VIH VIL VIL VIL X X R VIH VIH VIH Falling X X W Rising Rising Rising VIH X X WP X(1) X VIH X VIL VIL/VDD I/O0 - I/O7 Command Address Data input Data output X X
Bus operation Command input Address input Data input Data output Write protect Standby
1. WP must be VIH when issuing a program or erase command.
Table 5.
Bus Cycle 1
st
Address insertion(1)
I/O7 A7 VIL A19 A27 VIL I/O6 A6 VIL A18 A26 VIL I/O5 A5 VIL A17 A25 VIL I/O4 A4 VIL A16 A24 VIL I/O3 A3 A11 A15 A23 A31(2) I/O2 A2 A10 A14 A22 A30 I/O1 A1 A9 A13 A21 A29 I/O0 A0 A8 A12 A20 A28
2nd 3rd 4
th
5th
1. Any additional address input cycles will be ignored. 2. A31 is valid only for the NAND16GW3C2A.
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NAND08GW3C2A, NAND16GW3C2A Table 6. Address definitions
Address A0 - A11 A12 - A18 A19 - A31 Definition Column address Page address Block address
Bus operations
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Command set
NAND08GW3C2A, NAND16GW3C2A
5
Command set
All bus write operations to the device are interpreted by the command interface. The commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when the Command Latch Enable signal is High. Device operations are selected by writing specific commands to the Command Register. The two-step command sequences for Program and Erase operations are imposed to maximize data security. The commands are summarized in Table 7: Commands. Table 7. Commands
Bus write operations(1) Command Read Random Data Output Page Program (sequential input default) Multiplane Page Program Random Data Input Block Erase Multiplane Block Erase Reset Read Electronic Signature Read Status Register 1st cycle 00h 05h 80h 80h 85h 60h 60h FFh 90h 70h 2nd cycle 30h E0h 10h 11h - D0h 60h - - - 3rd cycle - - - 81h - - D0h - - - 4th cycle - - - 10h - - - - - - Yes Yes Commands accepted during busy
1. The bus cycles are only shown for issuing the codes. The cycles required to input the addresses or input/output data are not shown.
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NAND08GW3C2A, NAND16GW3C2A
Device operations
6
Device operations
This section gives the details of the device operations.
6.1
Read Memory Array
At power-up the device defaults to Read mode. To enter Read mode from another mode the Read command must be issued, see Table 7: Commands. Once a Read command is issued, subsequent consecutive Read commands only require the confirm command code (30h). Once a Read command is issued, two types of operations are available: Random Read and Page Read.
6.2
Random Read
Each time the Read command is issued, the first read is random-read.
6.3
Page Read
After the first random read access, the page data (2112 bytes) is transferred to the page buffer in a time of tWHBH (refer to Table 21 for value). Once the transfer is complete, the Ready/Busy signal goes High. The data can then be read out sequentially (from the selected column address to last column address) by pulsing the Read Enable signal. The device can output random data in a page, instead of the consecutive sequential data, by issuing a Random Data Output command. The Random Data Output command can be used to skip some data during a sequential data output. The sequential operation can be resumed by changing the column address of the next data to be output, to the address which follows the Random Data Output command.The Random Data Output command can be issued as many times as required within a page.
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Device operations Figure 7.
CL
NAND08GW3C2A, NAND16GW3C2A
Read operations
E
W
AL
R tBLBH1 RB
I/O
00h
Command Code
Address Input
30h
Command Code
Data Output (sequentially)
Busy Ai11016
1. Highest address depends on device density.
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NAND08GW3C2A, NAND16GW3C2A Figure 8. Random data output
Device operations
tBLBH1
(Read Busy time)
RB Busy
R
I/O
000h Cmd Code
Address Inputs
30h Cmd Code
Data Output
05h Cmd Code
Address Inputs
E0h Cmd Code
Data Output
5 Add cycles Row Add 1,2,3 Col Add 1,2 Spare Area
2Add cycles Col Add 1,2 Spare Area
Main Area
Main Area
ai08658b
6.4
Page Program
The Page Program operation is the standard operation to program data to the memory array. Generally, data is programmed sequentially, however, the device does support random input within a page. The memory array is programmed by page, however, partial page programming is allowed where any number of bytes (1 to 2112) can be programmed. Only one consecutive partial Page Program operation is allowed on the same page. After exceeding this a Block Erase command must be issued before any further Program operations can take place in that page.
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Device operations
NAND08GW3C2A, NAND16GW3C2A
6.5
Sequential Input
To input data sequentially the addresses must be sequential and remain in one block. For Sequential Input, each Page Program operation comprises five steps: 1. 2. 3. 4. 5. One bus cycle is required to set up the Page Program (Sequential Input) command (see Table 7). Five bus cycles are then required to input the program address (refer to Table 5). The data is loaded into the data registers. One bus cycle is required to issue the Page Program Confirm command to start the P/E/R controller. The P/E/R only starts if the data has been loaded in step 3. The P/E/R controller then programs the data into the array.
6.6
Random Data Input
During a Sequential Input operation, the next sequential address to be programmed can be replaced by a random address issuing a Random Data Input command. The following two steps are required to issue the command: 1. 2. One bus cycle is required to setup the Random Data Input command (see Table 7). Two bus cycles are then required to input the new column address (refer to Table 5).
Random Data Input can be repeated as often as required in any given page. Once the Program operation has started the Status Register can be read using the Read Status Register command. During program operations the status register only flags errors for bits set to `1' that have not been successfully programmed to `0'. During the Program operation, only the Read Status Register and Reset commands are accepted; all other commands are ignored. Once the Program operation has completed, the P/E/R controller bit SR6 is set to `1' and the Ready/Busy signal goes High. The device remains in Read Status Register mode until another valid command is written to the command interface. Figure 9. Page Program operation
(Program Busy time)
tBLBH2
RB Busy I/O 80h Page Program Setup Code Address Inputs Data Input 10h Confirm Code 70h SR0
Read Status Register
ai08659
24/58
NAND08GW3C2A, NAND16GW3C2A Figure 10. Random Data Input during Sequential Data Input
Device operations
(Program Busy time)
tBLBH2
RB Busy I/O 80h Cmd Code Address Inputs Data Intput 85h Cmd Code Address Inputs 2 Add cycles Col Add 1,2 Data Input 10h Confirm Code 70h SR0
Read Status Register
5 Add cycles Row Add 1,2,3 Col Add 1,2
Main Area
Spare Area
Main Area
Spare Area
ai08664
6.7
Multiplane Page Program
The devices support Multiplane Page Program, that allows the programming of two pages in parallel, one in each plane. A Multiplane Page Program operation requires two steps: 1. The first step loads serially up to two pages of data (4224 bytes) into the data buffer. It requires: - - - - One clock cycle to set up the Page Program command (see Section 6.5: Sequential Input). Five bus write cycles to input the first page address and data. The address of the first page must be within the first plane (A19 = 0). One bus write cycle to issue the Page Program Confirm code. After this the device is busy for a time of tBLBH5. When the device returns to the ready state (Ready/Busy High), a Multiplane Page Program Setup code must be issued, followed by the second page address (5 write cycles) and data. The address of the second page must be within the second plane (A19=1), and A18 to A12 must be the address bits loaded during the first address insertion.
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Device operations 2.
NAND08GW3C2A, NAND16GW3C2A
The second step programs, in parallel, the two pages of data loaded into the data buffer into the appropriate memory pages. It is started by issuing a Program Confirm command.
As for standard Page Program operations, the device supports Random Data Input during both data loading phases. Once the Multiplane Page Program operation has started, maintaining a delay of tBLBH5, the Status Register can be read using the Read Status Register command. Once the Multiplane Page Program operation has completed, the P/E/R controller bit SR6 is set to `1' and the Ready/Busy signal goes High. If the Multiplane Page Program fails, an error is signaled on bit SR0 of the Status Register. However, there is no way to identify for which page the program operation failed. See Figure 11 for a description of Multiplane Page Program waveforms. Figure 11. Multiplane Page Program
tBLBH5 RB Busy I/O 80h Address Inputs A19=0 Data Input 11h Confirm Code 81h Address Inputs A19=1 Data Input 10h Confirm Code Busy 70h SR0 tBLBH2
(Program Busy time)
Page Program Setup Code
Multiplane Page Program Setup code
Read Status Register
ai13636
6.8
Block Erase
Erase operations are done one block at a time. An Erase operation sets all of the bits in the addressed block to `1'. All previous data in the block is lost. An Erase operation consists of three steps (refer to Figure 12): 1. 2. 3. One bus cycle is required to setup the Block Erase command. Only addresses A19 to A31 are used; the other address inputs are ignored. Three bus cycles are then required to load the address of the block to be erased. Refer to Table 6 for the block addresses of each device. One bus cycle is required to issue the Block Erase Confirm command to start the P/E/R controller.
The Erase operation is initiated on the rising edge of write Enable, W, after the Confirm command is issued. The P/E/R Controller handles Block Erase and implements the verify process. During the Block Erase operation, only the Read Status Register and Reset commands are accepted; all other commands are ignored.
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NAND08GW3C2A, NAND16GW3C2A
Device operations
Once the program operation has completed, the P/E/R controller bit SR6 is set to `1' and the Ready/Busy signal goes High. If the operation completes successfully, the write status bit SR0 is `0', otherwise it is set to `1'. Figure 12. Block Erase operation
tBLBH3
(Erase Busy time)
RB Busy I/O 60h Block Erase Setup Code Block Address Inputs D0h Confirm Code 70h SR0
Read Status Register
ai07593
6.9
Multiplane Block Erase
The Multiplane Block Erase operation allows erasing two blocks in parallel, one in each plane. It consists of three steps (refer to Figure 13: Multiplane Block Erase operation): 1. Eight bus cycles are required to set up the Block Erase command and load the addresses of the blocks to be erased. The Setup command, followed by the address of the block to be erased, must be issued for each block. No dummy busy time is required between the first and second block address insertion. As for Multiplane Page Program, the address of the first and second page must be within the first plane (A19 = 0) and second plane (A19 = 1), respectively. One bus cycle is then required to issue the Multiplane Block Erase confirm command and start the P/E/R controller.
2.
If the Multiplane Block Erase fails, an error is signaled on bit SR0 of the status register. However, there is no way to identify for which page the Multiplane Block Erase operation failed. Figure 13. Multiplane Block Erase operation
tBLBH3
(Erase Busy time)
RB Busy I/O 60h Block Erase Setup Code Block Address Inputs A19=0 60h Block Erase Setup Code Block Address Inputs A19=1 D0h Confirm Code 70h SR0
Read Status Register
ai13637
27/58
Device operations
NAND08GW3C2A, NAND16GW3C2A
6.10
Reset
The Reset command is used to reset the command interface and Status Register. If the Reset command is issued during any operation, the operation is aborted. If it is a Program or Erase operation that is being aborted, the contents of the memory locations being modified are no longer valid as the data is partially programmed or erased. If the device has already been reset, then the new Reset command is not accepted. The Ready/Busy signal goes Low for tBLBH4 after the Reset command is issued. The value of tBLBH4 depends on the operation that the device was performing when the command was issued. Refer to Table 21 for the values.
6.11
Read Status Register
The device contains a Status Register that provides information on the current or previous Program or Erase operation. The various bits in the Status Register convey information and errors on the operation. The Status Register is read by issuing the Read Status Register command. The Status Register information is present on the output data bus (I/O0-I/O7) on the falling edge of Chip Enable or Read Enable, whichever occurs last. When several memories are connected in a system, the use of Chip Enable and Read Enable signals allows the system to poll each device separately, even when the Ready/Busy pins are common-wired. It is not necessary to toggle the Chip Enable or Read Enable signals to update the contents of the status register. After the Read Status Register command has been issued, the device remains in Read Status Register mode until another command is issued. Therefore, if a Read Status Register command is issued during a random read cycle a new Read command must be issued to continue with a Page Read operation. Refer to Table 8 which summarizes Status Register bits and should be read in conjunction with the following text descriptions.
6.11.1
Write protection bit (SR7)
The write protection bit can identify if the device is protected or not. If the write protection bit is set to `1' the device is not protected and Program or Erase operations are allowed. If the write protection bit is set to `0' the device is protected and Program or Erase operations are not allowed.
6.11.2
P/E/R controller bit (SR6)
Status register bit SR6 acts as a P/E/R controller bit, which indicates whether the P/E/R controller is active or inactive. When the P/E/R controller bit is set to `0', the P/E/R controller is active (device is busy); when the bit is set to `1', the P/E/R controller is inactive (device is ready).
6.11.3
Error bit (SR0)
The error bit is used to identify if any errors have been detected by the P/E/R controller. The error bit is set to `1' when a Program or Erase operation has failed to write the correct data to the memory. If the error bit is set to `0', the operation has completed successfully.
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NAND08GW3C2A, NAND16GW3C2A
Device operations
6.12
Table 8.
Bit SR7
SR5, SR4, SR3, SR2 and SR1 bits are reserved
Status Register bits
Name Write protection `0' `1' Protected P/E/R C inactive, device ready P/E/R C active, device busy Logic level `1' Not protected Definition
SR6 SR5, SR4, SR3, SR2, SR1 SR0
Program/erase/read controller `0' Reserved Don't care `1' Generic error `0' No error - operation successful Error - operation failed
6.13
Read Electronic Signature
The device contains a manufacturer code and device code. The following three steps are required to read these codes: 1. 2. 3. One bus write cycle to issue the Read Electronic Signature command (90h) One bus write cycle to input the address (00h) Four bus read cycles to sequentially output the data (as shown in Table 9: Electronic signature)
Table 9.
Electronic signature
Byte/word 1 Byte/word 2 Byte 3 Manufacturer code 20h Device code (see Table 10) Byte 4 (see Table 11) Byte 5 (see Table 12)
Part number
NAND08GW3C2A NAND16GW3C2A(1) D3h 14h A5h 6Ch
1. Each 8-Gbit die returns its own electronic signature.
29/58
Device operations Table 10.
I/O
NAND08GW3C2A, NAND16GW3C2A
Electronic signature byte 3
Definition Value 00 01 10 11 00 01 10 11 00 01 10 11 0 1 0 1 Description 1 2 4 8 2-level cell 4-level cell 8-level cell 16-level cell 1 2 4 8 Not supported Supported Not supported Supported
I/O1-I/O0
Internal chip number
I/O3-I/O2
Cell type
I/O5-I/O4
Number of simultaneously programmed pages
I/O6 I/O7
Interleaved programming between multiple devices Cache program
Table 11.
I/O
Electronic signature byte 4
Definition Value 00 01 10 11 0 1 00 10 01 11 00 01 10 11 0 1 Description 1 KBytes 2 Kbytes 4 Kbytes 8 Kbytes 8 16 30/50 ns 25 ns Reserved Reserved 64 Kbytes 128 Kbytes 256 Kbytes 512 Kbytes x8 x16
I/O1-I/O0
Page size (without spare area) Spare area size (byte/512 byte)
I/O2
I/O7, I/O3
Minimum sequential access time
I/O5-I/O4
Block size (without spare area)
I/O6
Organization
30/58
NAND08GW3C2A, NAND16GW3C2A Table 12. Electronic signature byte 5
I/O I/O1 - I/O0 Definition Reserved Value 00 0 0 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1
Device operations
Description
I/O3 - I/O2
Plane number
1 Plane 2 Planes 4 Planes 8 Planes 64 Mbits 128 Mbits 256 Mbits 512 Mbits 1 Gb 2 Gb 4 Gb 8 Gb
I/O6 - I/O4
Plane size (without spare area)
I/O7
Reserved
31/58
Concurrent operations and ERS on the NAND16GW3C2A
NAND08GW3C2A, NAND16GW3C2A
7
Concurrent operations and ERS on the NAND16GW3C2A
The NAND16GW3C2A is composed by two 8-Gbit dice stacked together. This configuration allows the device to support concurrent operations. This means that while performing an operation in one die (Erase, Read, Program, etc.), another operation is possible in the other die. The standard Read Status Register (ERS) operation returns the status of the NAND16GW3C2A device. To provide information on each 8-Gbit die, the NAND16GW3C2A features an Extended Read Status Register command that allows to check independently the status of each die. The following steps are required to perform concurrent operations: 1. 2. 3. 4. Select one of the two dice by setting the most significant address bit A31 to `0' or `1'. Execute one operation on this die. Launch a concurrent operation on the other die. Check the status of these operations by performing an Extended Read Status Register operation.
All combinations of operations are possible except executing Read on both dice. This is due to the fact that the input/output bus is common to both dice. Refer to Table 13 for the description of the Extended Read Status Register command sequence, and to Table 8. for the definition of the Status Register bits. Table 13. Extended Read Status Register commands
Address range Address 0x7FFFFFFF 0x7FFFFFFF < Address 0xFFFFFFF 1 bus write cycle F1h F2h
Command Read 1st die status Read 2nd die status
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NAND08GW3C2A, NAND16GW3C2A
Data protection
8
Data protection
The device has hardware features to protect against Program and Erase operations. It features a Write Protect, WP, pin, which protects the device against program and erase operations. It is recommended to keep WP at VIL during power-up and power-down.
9
Software algorithms
This section gives information on the software algorithms that Numonyx recommends implementing to manage the bad blocks and extend the lifetime of the NAND device. NAND Flash memories are programmed and erased by Fowler-Nordheim tunneling using high voltage. Exposing the device to high voltage for extended periods can cause the oxide layer to be damaged. For this reason, the number of program and erase cycles is limited (see Table 15 for value). It is recommended to implement garbage collection, wear-leveling and error correction code algorithms to extend the number of program and erase cycles and to increase data retention. To help integrate a NAND memory into an application Numonyx can provide a File System OS Native reference software, which supports the basic commands of file management. Contact the nearest Numonyx sales office for more details.
9.1
Bad block management
Devices with bad blocks have the same quality level and the same AC and DC characteristics as devices where all the blocks are valid. A bad block does not affect the performance of valid blocks because it is isolated from the bit line and common source line by a select transistor. The devices are supplied with all the locations inside valid blocks erased (FFh). The bad block information is written prior to shipping. Any block, where the 1st byte in the spare area of the last page, does not contain FFh, is a bad block. The bad block information must be read before any erase is attempted as the bad block Information may be erased. For the system to be able to recognize the bad blocks based on the original information it is recommended to create a bad block table following the flowchart shown in Figure 14.
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Software algorithms
NAND08GW3C2A, NAND16GW3C2A
9.2
NAND Flash memory failure modes
The NAND08GW3C2A and NAND16GW3C2A devices may contain bad blocks, where the reliability of blocks that contain one or more invalid bits is not guaranteed. Additional bad blocks may develop during the lifetime of the device. To implement a highly reliable system, all the possible failure modes must be considered:
Program/erase failure in this case, the block has to be replaced by copying the data to a valid block. These additional bad blocks can be identified as attempts to program or erase them and will give errors in the Status Register. Because the failure of a Page Program operation does not affect the data in other pages in the same block, the block can be replaced by re-programming the current data and copying the rest of the replaced block to an available valid block. The Copy Back Program command can be used to copy the data to a valid block. See Section Figure 10.: Random Data Input during Sequential Data Input for more details.
Read failure in this case, ECC correction must be implemented. To efficiently use the memory space, it is recommended to recover single-bit errors in read by ECC, without replacing the whole block.
Refer to Table 14 for the procedure to follow if an error occurs during an operation. Table 14. Block failure
Operation Erase Program Read Procedure Block replacement Block replacement or ECC (with 4 bit/528 byte) ECC (with 4 bit/528 byte)
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NAND08GW3C2A, NAND16GW3C2A Figure 14. Bad block management flowchart
START
Software algorithms
Block Address = Block 0
Increment Block Address Update Bad Block table
Data = FFh? YES
NO
Last block? YES
NO
END
AI07588C
9.3
Garbage collection
When a data page needs to be modified, it is faster to write to the first available page and mark the previous page as invalid. After several updates it is necessary to remove invalid pages to free some memory space. To free this memory space and allow further program operations, it is recommended to implement a garbage collection algorithm. In a garbage collection software the valid pages are copied into a free area and the block containing the invalid pages is erased (see Figure 15).
Figure 15. Garbage collection
Old Area New Area (After GC)
Valid Page Invalid Page Free Page (Erased)
AI07599B
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Software algorithms
NAND08GW3C2A, NAND16GW3C2A
9.4
Wear-leveling algorithm
For write-intensive applications, it is recommended to implement a wear-leveling algorithm to monitor and spread the number of write cycles per block. In memories that do not use a wear-leveling algorithm, not all blocks get used at the same rate. The wear-leveling algorithm ensures that equal use is made of all the available write cycles for each block. There are two wear-leveling levels: 1. 2. First level wear-leveling, where new data is programmed to the free blocks that have had the fewest write cycles Second level wear-leveling, where long-lived data is copied to another block so that the original block can be used for more frequently changed data.
The second level wear-leveling is triggered when the difference between the maximum and the minimum number of write cycles per block reaches a specific threshold.
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NAND08GW3C2A, NAND16GW3C2A
Software algorithms
9.5
9.5.1
Hardware simulation models
Behavioral simulation models
Denali Software Corporation models are platform-independent functional models designed to assist customers in performing entire system simulations (typical VHDL/Verilog). These models describe the logic behavior and timings of NAND Flash devices, and, therefore, allow software to be developed before hardware.
9.5.2
IBIS simulations models
I/O buffer information specification (IBIS) models describe the behavior of the I/O buffers and electrical characteristics of Flash devices. These models provide information such as AC characteristics, rise/fall times, and package mechanical data, all of which are measured or simulated at voltage and temperature ranges wider than those allowed by target specifications. IBIS models are used to simulate PCB connections and can be used to resolve compatibility issues when upgrading devices. They can be imported into SPICETOOLS.
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Program and erase times and endurance cycles
NAND08GW3C2A, NAND16GW3C2A
10
Program and erase times and endurance cycles
Table 15 shows the program and erase times and the number of program/erase cycles per block. Table 15. Program and erase times and program erase endurance cycles
NAND08GW3C2A, NAND16GW3C2A Parameters Min Page program time Block erase time Program/erase cycles (per block (with ECC) Data retention 10,000 10 Typ 800 2.5 Max 2000 3 s ms cycles years Unit
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NAND08GW3C2A, NAND16GW3C2A
Maximum ratings
11
Maximum ratings
Stressing the device above the ratings listed in Table 16: Absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the Numonyx SURE Program and other relevant quality documents. Table 16.
Symbol TBIAS TSTG VIO(1) VDD
Absolute maximum ratings
Value Parameter Min Temperature under bias Storage temperature Input or output voltage Supply voltage - 50 - 65 - 0.6 - 0.6 Max 125 150 4.6 4.6 C C V V Unit
1. Minimum voltage may undershoot to -2 V for less than 20 ns during transitions on input and I/O pins. Maximum voltage may overshoot to VDD + 2 V for less than 20 ns during transitions on I/O pins.
39/58
DC and AC parameters
NAND08GW3C2A, NAND16GW3C2A
12
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC characteristics tables are derived from tests performed under the measurement conditions summarized in Table 17: Operating and ac measurement conditions. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 17. Operating and ac measurement conditions
Parameter NAND08GW3C2A, NAND16GW3C2A Min Supply voltage (VDD) Ambient temperature (TA) Load capacitance (CL) (1 TTL GATE and CL) Input pulses voltages Input and output timing ref. voltages Output circuit resistor Rref Input rise and fall times 0.4 1.5 8.35 5 2.7 0 -40 50 2.4 Max 3.6 70 85 V C C pF V V k ns Units
Table 18.
Symbol CIN CI/O
Capacitance(1)
Parameter Input capacitance Input/output capacitance Test condition VIN = 0 V VIL = 0 V Typ Max 10 10 Unit pF pF
1. TA = 25 C, f = 1 MHz. CIN and CI/O are not 100% tested.
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NAND08GW3C2A, NAND16GW3C2A Table 19.
Symbol IDD1 IDD2 IDD3
IDD4
DC and AC parameters
DC characteristics
Parameter Sequential read Program Erase Standby current (TTL) Standby current (CMOS) Input leakage Current Output leakage Current Input high voltage Input low voltage Output high voltage level Output low voltage level Output low current (RB) Test conditions tRLRL minimum E=VIL, IOUT = 0 mA E=VIH, WP=0/VDD E=VDD-0.2, WP=0/VDD VIN= 0 to 3.6V VOUT= 0 to 3.6V IOH = -400A IOL = 2.1mA VOL = 0.4V 2.0 -0.3 2.4 8 10 10 Min Typ 15 15 15 Max 30 30 30 1 50 10 10 VDD+0.3 0.8 0.4 Unit mA mA mA mA A A A V V V V mA
Operating current
IDD5 ILI ILO VIH VIL VOH VOL IOL (RB)
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DC and AC parameters Table 20.
Symbol tALLWH tALHWH tCLHWH tCLLWH tDVWH tELWH tWHALH tWHALL tWHCLH tWHCLL tWHDX tWHEH tWHWL tWLWH tWLWL
NAND08GW3C2A, NAND16GW3C2A
AC characteristics for command, address, data input
Alt. symbol tALS Parameter Address Latch Low to Write Enable High AL setup time Address Latch High to Write Enable High Command Latch High to Write Enable High tCLS tDS tCS tALH CL setup time Command Latch Low to Write Enable High Data Valid to Write Enable High Chip Enable Low to Write Enable High Write Enable High to Address Latch High AL hold time Write Enable High to Address Latch Low Write Enable High to Command Latch High tCLH tDH tCH tWH tWP tWC CL hold time Write Enable High to Command Latch Low Write Enable High to Data Transition Write Enable High to Chip Enable High Write Enable High to Write Enable Low Write Enable Low to Write Enable High Write Enable Low to Write Enable Low Data hold time E hold time Min Min 5 5 10 12 25 ns ns ns ns ns Min 5 ns Min 5 ns Data setup time E setup time Min Min 12 20 ns ns Min 12 ns Min 12 ns Value Unit
W High hold time Min W pulse width Write cycle time Min Min
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NAND08GW3C2A, NAND16GW3C2A Table 21.
Symbol tALLRL1 tALLRL2 tBHRL tBLBH1 tBLBH2 tBLBH3 tPROG tBERS Ready/Busy Low to Ready/Busy High
DC and AC parameters
AC characteristics for operations
Alt. Symbol Value Parameter Min Typ Max Address Latch Low to Read Enable Low Read Electronic Signature Read cycle 10 10 20 60 2000 3 5 5 10 500 1 10 0 30 25 10 15 15 5 100 12 25 20 60 100 80 70 100 tWW Write Protection time 100 ns 2 ns ns ns s s ms s s s s s ns ns ns ns ns ns ns ns ns ns ns ns s ns ns ns ns Unit
tAR tRR
Ready/Busy High to Read Enable Low Read Busy time Program Busy time Erase Busy time Reset Busy time, during ready Reset Busy time, during read
tBLBH4
tRST
Reset Busy time, during program Reset Busy time, during erase
tBLBH5 tCLLRL tDZRL tEHQZ tELQV tRHRL tEHQX tRHQX tRLQX tRHQZ tRLRH tRLRL tRLQV tWHBH tWHBL tWHRL tWHWH(2) tVHWH tVLWH
(3) (3)
tCBSY tCLR tIR tCHZ tCEA tREH tCOH tRHOH tRLOH tRHZ tRP tRC tREA tR tWB tWHR tADL
Dummy Busy Time for Multiplane operations Command Latch Low to Read Enable Low Data Hi-Z to Read Enable Low Chip Enable High to Output Hi-Z Chip Enable Low to Output Valid Read Enable High to Read Enable Low Chip Enable High to Output Hold Read Enable High to Output Hold Read Enable Low to Output Hold (EDO Mode) Read Enable High to Output Hi-Z Read Enable Low to Read Enable High Read Enable Low to Read Enable Low Read Enable Low to Output Valid Write Enable High to Ready/Busy High Read Enable Pulse Width Read Cycle time Read Enable Access time Read ES Access time(1) Read Busy time Read Enable High Hold time
Write Enable High to Ready/Busy Low Write Enable High to Read Enable Low Last Address latched on Data Loading Time during Program operations
1. ES = Electronic Signature. 2. tWHWH is the delay from Write Enable rising edge during the final address cycle to Write Enable rising edge during the first data cycle. 3. WP High to W High during Program/Erase Enable operations.
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DC and AC parameters Figure 16. Command latch AC waveforms
CL tCLHWH
(CL Setup time)
NAND08GW3C2A, NAND16GW3C2A
tWHCLL
(CL Hold time)
tELWH
H(E Setup time)
tWHEH
(E Hold time)
E tWLWH W tALLWH
(ALSetup time)
tWHALH
(AL Hold time)
AL tDVWH
(Data Setup time)
tWHDX
(Data Hold time)
I/O
Command
ai12470b
Figure 17. Address latch AC waveforms
(CL Setup time)
tCLLWH
CL tELWH
(E Setup time)
tWLWL
tWLWL
tWLWL
tWLWL
E tWLWH W tWHWL tALHWH
(AL Setup time)
tWLWH
tWLWH
tWLWH
tWLWH
tWHWL
tWHWL
tWHWL
tWHALL
(AL Hold time)
tWHALL
tWHALL
tWHALL
AL tDVWH tDVWH tWHDX
(Data Hold time)
(Data Setup time)
tDVWH tWHDX Adrress cycle 2 Adrress cycle 3
tDVWH tWHDX Adrress cycle 4
tDVWH tWHDX Adrress cycle 5
ai12471
tWHDX
I/O
Adrress cycle 1
44/58
NAND08GW3C2A, NAND16GW3C2A Figure 18. Data input latch AC waveforms
DC and AC parameters
tWHCLH
(CL Hold time)
CL tWHEH
(E Hold time)
E
(ALSetup time)
tALLWH
tWLWL AL tWLWH W tDVWH
(Data Setup time)
tWLWH
tWLWH
tDVWH tWHDX
(Data Hold time)
tDVWH tWHDX tWHDX
I/O
Data In 0
Data In 1
Data In Last
ai12472
1. The last data input is the 2112th.
Figure 19. Sequential data output after Read AC waveforms
tRLRL
(Read Cycle time)
E tEHQX tRHRL R
(R High Holdtime)
tEHQZ
tRHQZ tRLQV
(R Accesstime)
tRHQZ tRLQV tRHQX(2)
tRLQV
I/O tBHRL RB
Data Out
Data Out
Data Out
ai13174
1. CL = Low, AL = Low, W = High. 2. tRHQX is applicable for frequencies lower than 33 MHz (i.e. tRLRL higher than 30 ns).
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DC and AC parameters
NAND08GW3C2A, NAND16GW3C2A
Figure 20. Sequential data output after Read AC waveforms (EDO mode)
tRLRL E tEHQX tRLRH R tELQV tRLQV
(R Accesstime)
tRHRL
tEHQZ
tRLQX tRLQV
tRHQZ tRHQX(2)
I/O tBHRL RB
Data Out
Data Out
Data Out
ai13175
1. In EDO mode, CL and AL are Low, VIL, and W is High, VIH. 2. tRLQX is applicable for frequencies higher than 33 MHz (i.e. tRLRL lower than 30 ns).
Figure 21. Read Status Register AC waveform
tCLLRL CL tWHCLL tCLHWH E tELWH tWLWH W tWHRL R tDZRL tDVWH
(Data Setup time)
tWHEH
tELQV
tEHQZ tEHQX
tRHQZ tRLQV tRHQX
tWHDX
(Data Hold time)
I/O
70h or 7Bh
Status Register Output
ai13177
46/58
NAND08GW3C2A, NAND16GW3C2A Figure 22. Read electronic signature AC waveform
CL
DC and AC parameters
E
W
AL tALLRL1
R
(Read ES Access time)
tRLQV
I/O
90h Read Electronic Signature Command
00h 1st Cycle Address
Byte1 Man. code
Byte2 Device code
Byte3
Byte4
Byte5
see Note.1
ai13178
1. Refer to Table 9 for the values of the manufacturer and device codes, and to Table 10, Table 11, and Table 12 for the information contained in byte 3, byte 4, and byte 5.
47/58
DC and AC parameters Figure 23. Page Read operation AC waveform
NAND08GW3C2A, NAND16GW3C2A
CL
E tWLWL W tWHBL AL tALLRL2 tWHBH tRLRL
(Read Cycle time)
tEHQZ
tRHQZ
R tRLRH tBLBH1 RB
I/O
00h
Add.N cycle 1
Add.N cycle 2
Add.N cycle 3
Add.N cycle 4
Add.N cycle 5
30h
Data N
Data N+1
Data N+2
Data Last
Command Code
Address N Input
Busy
Data Output from Address N to Last Byte or Word in Page
ai13638
48/58
NAND08GW3C2A, NAND16GW3C2A Figure 24. Page Program AC waveform
DC and AC parameters
CL
E tWLWL
(Write Cycle time)
tWLWL
tWLWL
W tWHWH tWHBL tBLBH2
(Program Busy time)
AL
R
I/O
80h
Add.N cycle 1
Add.N cycle 2
Add.N Add.N Add.N cycle 3 cycle 4 cycle 5
N
Last
10h
70h
SR0
RB Page Program Setup Code Confirm Code
Address Input
Data Input
Page Program Read Status Register
ai13639
49/58
DC and AC parameters Figure 25. Block Erase AC waveform
NAND08GW3C2A, NAND16GW3C2A
CL
E tWLWL
(Write Cycle time)
W tWHBL AL
(Erase Busy time)
tBLBH3
R
I/O
60h
Add. Add. Add. cycle 1 cycle 2 cycle 3
D0h
70h
SR0
RB Block Erase Setup Command Confirm Code Block Erase Read Status Register
ai08038c
Block Address Input
Figure 26. Reset AC waveform
W
AL CL
R I/O FFh tBLBH4
(Reset Busy time)
RB
ai08043
50/58
NAND08GW3C2A, NAND16GW3C2A Figure 27. Program/Erase Enable waveform
DC and AC parameters
W tVHWH WP
RB
I/O
80h
10h
ai12477
Figure 28. Program/Erase Disable waveform
W tVLWH WP High RB
I/O
80h
10h
ai12478
51/58
DC and AC parameters
NAND08GW3C2A, NAND16GW3C2A
12.1
Ready/Busy signal electrical characteristics
Figure 30, Figure 29 and Figure 31 show the electrical characteristics for the Ready/Busy signal. The value required for the resistor RP can be calculated using the following equation:
(V - ) DDmax V OLmax R P min = ------------------------------------------------------------I OL + I L
So,
3.2V R P min = -------------------------8mA + I L
where IL is the sum of the input currents of all the devices tied to the Ready/Busy signal. RP max is determined by the maximum value of tr. Figure 29. Ready/Busy AC waveform
ready VDD VOH VOL busy tf tr
AI07564B
Figure 30. Ready/Busy load circuit
VDD
RP
ibusy
DEVICE RB Open Drain Output
VSS
AI07563B
52/58
NAND08GW3C2A, NAND16GW3C2A
DC and AC parameters
Figure 31. Resistor value versus waveform timings for Ready/Busy signal
VDD = 3.3 V, CL = 50 pF 200
200 2.4
4
150
tr, tf (ns)
1.2
150
3
ibusy (mA)
100
100 0.8
2
50
50 1.8 1.8
1
0.6 1.8
0
1.8
1
2 RP (K) tf tr
3
4
ibusy
a
1. T = 25C.
12.2
Data protection
The Numonyx NAND device is designed to guarantee data protection during power transitions. A VDD detection circuit disables all NAND operations, if VDD is below the VLKO threshold. In the VDD range from VLKO to the lower limit of nominal range, the WP pin should be kept Low (VIL) to guarantee hardware protection during power transitions as shown in Figure 32. Figure 32. Data protection
VDD
Nominal Range
VLKO
Locked
Locked
W
Ai11086
53/58
Package mechanical
NAND08GW3C2A, NAND16GW3C2A
13
Package mechanical
This section contains mechanical data for the packages.
Figure 33. TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline
1 48
e
D1
B
24
25
L1 A2 A
E1 E
DIE
A1 C CP
L
TSOP-G
1. Drawing is not to scale.
Table 22.
Symbol
TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package mechanical data
millimeters Typ Min Max 1.200 0.100 1.000 0.220 0.050 0.950 0.170 0.100 0.150 1.050 0.270 0.210 0.080 12.000 20.000 18.400 0.500 0.600 0.800 3 0 5 11.900 19.800 18.300 - 0.500 12.100 20.200 18.500 - 0.700 0.4724 0.7874 0.7244 0.0197 0.0236 0.0315 3 0 5 0.4685 0.7795 0.7205 - 0.0197 0.0276 0.0039 0.0394 0.0087 0.0020 0.0374 0.0067 0.0039 Typ inches Min Max 0.0472 0.0059 0.0413 0.0106 0.0083 0.0031 0.4764 0.7953 0.7283
A A1 A2 B C CP D1 E E1 e L L1 a
54/58
NAND08GW3C2A, NAND16GW3C2A Figure 34. LGA52 12 x 17 mm, 1 mm pitch, package outline
D D2 D1 FE1 FE FD FD1
Package mechanical
BALL "A1"
eE1
E E2
E1 e ddd
e A
b1 b2 A2
LGA-9G
Table 23.
LGA52 12 x 17 mm, 1 mm pitch, package mechanical data
millimeters inches Max 0.650 0.650 0.700 1.000 12.000 6.000 10.000 0.100 17.000 12.000 13.000 1.000 2.000 3.000 1.000 2.500 2.000 - - - - 16.900 17.100 0.6693 0.4724 0.5118 0.0394 0.0787 0.1181 0.0394 0.0984 0.0787 - - - - 0.6654 0.650 0.950 11.900 0.750 1.050 12.100 0.0276 0.0394 0.4724 0.2362 0.3937 0.0039 0.6732 0.0256 0.0374 0.4685 Typ Min Max 0.0256 0.0256 0.0295 0.0413 0.4764
Symbol Typ A A2 b1 b2 D D1 D2 ddd E E1 E2 e eE1 FD FD1 FE FE1 Min
55/58
Ordering information
NAND08GW3C2A, NAND16GW3C2A
14
Ordering information
Table 24.
Example: Device type NAND Flash memory Density 08G = 8 Gbits 16G = 16 Gbits Operating voltage W = VDD = 2.7 to 3.6 V Bus width 3=x8 Family identifier C = 2112 bytes Page MLC Device options 2 = Chip Enable Don't Care Enabled 4 = Chip Enable Don't Care Enabled with 2 Chip Enable and 2 Ready/Busy signals Product version A = First version Package N = TSOP48 12 x 20 mm ZL = ULGA52 12 x 17 mm Temperature range 1 = 0 to 70 C 6 = -40 to 85 C Option E = ECOPACK(R) package, standard packing F = ECOPACK(R) package, tape & reel packing
Ordering information scheme
NAND08G W 3 C2A N1 E
Devices are shipped from the factory with the memory content bits, in valid blocks, erased to `1'. For further information on any aspect of this device, please contact your nearest Numonyx Sales Office.
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NAND08GW3C2A, NAND16GW3C2A
Revision history
15
Revision history
Table 25.
Date 22-Dec-2006
Document revision history
Revision 0.1 Initial release. - Changed throughout the document "NAND16GW3C2A" to "NAND16GW3C4A. - Listed throughout document the details relating to the two 8-Gbit dice, the two Chip Enable, and two Ready/Busy signals in the NAND16GZ3C4A, which required changes in several figures and tables. - Added power-up and power-down minimum recovery time information in Section 3.8: Ready/Busy (RB1, RB2). - Added program and read information in Section Table 14.: Block failure. - Modified page program time parameters and program/erase cycles parameters in Section Table 15.: Program and erase times and program erase endurance cycles. - Modified AC characteristics in Section Table 21.: AC characteristics for operations. Applied Numonyx branding. Changes
11-Jun-2007
1
04-Jan-2008
2
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NAND08GW3C2A, NAND16GW3C2A
Please Read Carefully:
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYXTM PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Numonyx may make changes to specifications and product descriptions at any time, without notice. Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at http://www.numonyx.com. Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright (c) 11/5/7, Numonyx B.V. All Rights Reserved.
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